Huafeng Yu @ INRIA Rennes

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Huafeng Yu is currently an expert research engineer in the ESPRESSO team at INRIA Rennes - Bretagne Atlantique / IRISA.  His current work is involved in the temporal analysis and simulation of MARTE timed systems, AADL, and Simulink in the framework of European CESAR project. He received his Ph.D. degree in computer science from Université des Sciences et Technologies de Lille 1 (USTL, in France) in November, 2008. During his Ph.D. study, he worked in the DaRT team at INRIA Lille-Nord Europe, France. He completed his Master's study in systems and softwares at Université Joseph Fourier (UJF, Grenoble 1, in France) in 2005. Before his Master study, he had been working in Panasonic and Gemplus as a software engineer for three years in China.


Contact

     Office C311,
     IRISA / INRIA Rennes,
     Campus de Beaulieu,
     263, avenue du Général Leclerc,
     35042 Rennes, France

     Tel:       +33 (0)2 99 84 75 41
     Fax:      +33 (0)2 99 84 71 71
     Mail:    huafeng.yu@inria.fr / huafeng.yu@gmail.com


Research interests

  • Embedded systems design
  • Formal verification, discrete controller synthesis
  • Model-Driven Engineering (MDE)
  • Programming languages

Recent publications

Modélisation compositionnelle d’architectures GALS dans un modèle de calcul polychrone
(Compositional Modeling of GASL Architecutre in a Polychronous Model of Computation)
Y. Ma, T. Gautier, J.-P. Talpin, P.  Le Guernic, and Huafeng Yu
In the Modélisation des Systèmes Réactifs (MSR'11, Modeling of reactive systems)
Lille, France. Nov. 16-18, 2011. To appear.
Journal Européen des Systèmes Automatisés (JESA). 45/1-3:61-76, DOI:10.3166/jesa.45.61-76
Lavoisier, 2011
Online version  DOI  HAL

Co-simulation of Embedded Software Architectures Using Polychrony
Huafeng Yu, Y. Ma, J.-P. Talpin, T. Gautier, L. Besnard, and P. Le Guernic
In the ETR 2011 (Ecole d'été Temps Réel),
Aug. 29st - Sep. 2nd 2011, Université de Bretagne Occidentale, Brest.

System Synthesis from AADL using Polychrony
Y. Ma, Huafeng Yu, T. Gautier, J-P Talpin, L. Besnard, and P. Le Guernic
In the 2011 Electronic System Level Synthesis Conference (ESLSYN'11)
San Diego, California, USA. June 5-6, 2011.
Online version  HAL  DOI

Polychronous Controller Synthesis from MARTE CCSL Timing Specifications
Huafeng Yu, J.-P. Talpin, L. Besnard, T. Gautier, H. Marchand, and P. Le Guernic
In the ACM/IEEE Ninth Int. Conf. on Formal Methods and Models for Codesign (MEMOCODE'11), 21-30
Cambridge, UK.  2011.
Online version  HAL  DOI

System-level Co-simulation of Integrated Avionics Using Polychrony
Huafeng Yu, Y. Ma, Y. Glouche, J.-P. Talpin, L. Besnard, T. Gautier, P. Le Guernic, A. Toom, and O. Laurent
In the 26th ACM Symposium On Applied Computing (SAC'11), 354-359
TaiChung, Taiwan. 2011.

Polychronous Analysis of Timing Constraints in UML MARTE
Huafeng Yu, J.-P. Talpin, L. Besnard, T. Gautier, F. Mallet, C. André, and R. de Simone
IEEE International Workshop on Model-Based Engineering for Real-Time Embedded Systems Design
(MoBE-RTES 2010, hosted by ISORC 2010).
Parador of Carmona, Spain. May 2010.