Ph.D. Thesis Hsiu-Ming (Sherman) Chang, Low-Cost Quality Assurance Techniques for Mixed-Signal/RF Circuits and Systems, University of California, Santa Barbara, March 2011. (Seminar Announcement and Abstract)(Ph.D. defense video) Journal Articles [J6] Hsiu-Ming (Sherman) Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, and Cheng-Wen Wu , "A Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers," accepted to be publish in IEEE Transactions on Very Large Scale Integration Systems. [J5] Hsiu-Ming (Sherman) Chang, Kuan-Yu Lin, and Kwang-Ting Cheng, “Tester-Assisted Calibration and Screening for Digitally-Calibrated ADCs,” IEEE Transactions on Circuits and Systems I – Regular Papers, vol. 58, no. 12, pp. 2838 - 2848, December 2011. (IEEEXplore) [J4] Ming Gao, Hsiu-Ming (Sherman) Chang, Peter Lisherness, and Kwang-Ting (Tim) Cheng, "Time-Multiplexed Online Checking", IEEE Transactions on Computer, vol. 60, no. 9, pp. 1300-1312, September 2011. (IEEEXplore) [J3] Hsiu-Ming (Sherman) Chang, Kuan-Yu Lin, and Kwang-Ting (Tim) Cheng, "Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study," Journal of Electronic Testing - Theory and Application (Special Issue on Analog, Mixed-Signal and RF Testing), vol. 26, no. 1, pp. 59-71, February 2010 . (SpringerLink) [J2] Kwang-Ting (Tim) Cheng and Hsiu-Ming (Sherman) Chang, "Recent Advances in Analog, Mixed-Signal, and RF Testing," IPSJ Transactions on System LSI Design Methodology (TSLDM), vol. 3, pp. 19-46, February 2010. (invited) (IPSJ TSLDM Site) [J1] Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, and Hsiu-Ming (Sherman) Chang , "A Digital Intensive Fractional-N PLL and All Digital Self-Calibration Schemes," IEEE J. of Solid-State Circuits (JSSC), vol. 44, no. 8,
pp. 2182
- 2192,
August 2009. (IEEEXplore) Conference Papers [C16] Hsiu-Ming (Sherman) Chang, Kwang-Ting (Tim) Cheng, Wangyang Zhang, Xi Li, and Kenneth Bulter, “Test Test Cost Reduction Through Performance Prediction Using Virtual Probe,” in Proceedings of 2011 International Test Conference (ITC2011), Anaheim, CA, Sept. 2011. [C15] Hsiu-Ming (Sherman) Cheng and Kwang-Ting (Tim) Cheng, "Image-Quality-Aware Metrics for Performance Specification of ADC Array in 3-D CMOS Imagers," in Proceedings of 48th IEEE/ACM Design Automation Conference (DAC2011), San Diego, CA, June 2011. (Certificate of Appreciation) [C14] Hsiu-Ming (Sherman) Cheng, Kwang-Ting (Tim) Cheng, and Jiun-Lang Huang, “Image-Quality-Driven Metrics for Testing and Calibrating ADC Array in CMOS Imagers: A First Step,” in Proceedings of 17th International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW2011), Santa Barbara, CA, May 2011. [C13] Ping-Ying Wang, Hsiu-Ming (Sherman) Chang, and Kwang-Ting (Tim) Cheng, “An All-Digital Built-in Self-Test Technique for Transfer Function Characterization of RF PLLs,” in Proceedings of Design, Automation and Test in Europe (DATE2011), Grenoble, France, March 2011. [C12] Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming (Sherman) Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, and Cheng-Wen Wu, “A Self-Testing and Calibration Method for Embedded Successive Approximation Register ADC,” in Proceedings of Asian-Pacific Design Automation Conference (ASP-DAC2011), pp. 713-718, Yokohama, Japan, Jan. 2011. [C11] Hsiu-Ming (Sherman) Chang and Kwang-Ting (Tim) Cheng, "Low-Cost Quality Assurance Techniques for Mixed-Signal/RF Circuits and Systems," in Proceedings of IEEE International Test Conference (ITC2010), L2.1., pp. 1-10, Austin, Texas, Nov. 2010. (invited) (Certificate of Appreciation) [C10] Hsiu-Ming (Sherman) Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, and Cheng-Wen Wu, "An Error Tolerance Scheme for 3D CMOS Imagers," in Proceedings of 47th IEEE/ACM Design Automation Conference (DAC2010), pp.917-922, Anaheim, CA, June 2010. (Certificate of Appreciation) [C9] Hsiu-Ming (Sherman) Chang, Kuan-Yu Lin, and Kwang-Ting (Tim) Cheng, "Calibration-Assisted Production Testing for Digitally-Calibrated ADCs," in Proceedings of 28th VLSI Test Symposium (VTS2010), pp. 295-300, Santa Cruz, California, April 2010. [C8] Hsiu-Ming (Sherman) Chang, Kuan-Yu Lin, and Kwang-Ting (Tim) Cheng, "Calibration as a Functional Test: An ADC Case Study," in Proceedings of 18th Asian Test Symposium (ATS2009), pp.85-86, TaiChung, Taiwan, November 2009. [C7] Kwang-Ting (Tim) Cheng and Hsiu-Ming (Sherman) Chang, "Test Strategies for Adaptive Equalizers," in Proceedings of the 29th Custom Integrated Circuits Conference (CICC2009), pp. 597-603, San Jose, September 2009. (invited) [C6] Hsiu-Ming (Sherman) Chang and Kwang-Ting (Tim) Cheng, "TAC: Testing Time Reduction for Digitally-Calibrated Designs," in Proceedings of 15th IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW2009), pp. 1-6, Scottsdale, Arizona, June 2009. [C5] Hsiu-Ming (Sherman) Chang, Chin-Hsuan Chen, Kuan-Yu Lin, and Kwang-Ting (Tim) Cheng, "Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC, " in Proceedings of 27th IEEE VLSI Test Symposium (VTS2009), pp. 291-296, Santa Cruz, California, May 2009. [C4] Hsiu-Ming (Sherman) Chang, Kuan-Yu Lin, Chin-Hsuan Chen, and Kwang-Ting (Tim) Cheng, "A Built-In Self-Calibration Scheme for Pipelined ADCs," in Proceedings of 10th IEEE International Symposium on Quality Electronics Design (ISQED2009), pp. 266-271, San Jose, California, March 2009. [C3] Hsiu-Ming (Sherman) Chang, Min-Sheng (Mitchell) Lin, and Kwang-Ting (Tim) Cheng, "Digitally-Assisted Analog/RF Testing for Mixed-Signal SoCs," in Proceedings of 17th Asian Test Symposium (ATS2008) , pp.43-48, Sapporo, November 2008. [C2] Ming Gao, Hsiu-Ming (Sherman) Chang, Peter
Lisherness, and Kwang-Ting (Tim) Cheng, "Time-Multiplexed Online Checking:
A Feasibility Study," in Proceedings of 17th Asian Test Symposium
(ATS2008) , pp. 371-376, Sapporo, November 2008.(IEEEXplore)(Project page and demo by Ming Gao) |