l Cost-Effective Test Techniques and Strategies for Digitally-Calibrated Analog Designs In [1-7], we develop production test techniques and strategies for digitally-calibrated analog designs. For the case study of a digitally-calibrated pipelined analog-to-digital converter (ADC), the proposed solution reduces the test time by more than 65%, in comparison with the conventional test methodology. This overall test time reduction is achieved by two key ideas: 1) drastic reduction of the calibration time required prior to the specification testing and 2) effective pre-test screening for early rejection. Methods for calibration time reduction are described in [3, 4, 7] which include accelerating the calibration process [3, 7] and terminating the calibration process at convergence [4, 7]. Calibration can be considered as an iterative process of testing and performance tuning. Therefore, we show in [5] that data gathered during calibration could be used to predict circuit performance without extra test time. This methodology of using calibration data for performance prediction, named digitally-assisted analog testing, was first introduced in [1] in which a case study of an RF receiver was demonstrated. We have also developed techniques to predict the static [6] and dynamic [2] performances of an ADC using calibration data. The prediction results can be used to pre-screen bad chips immediately after calibration, which results in significant reduction of test time and cost. Related Publications: [1] Hsiu-Ming (Sherman) Chang, Min-Sheng (Mitchell) Lin, and Kwang-Ting (Tim) Cheng, "Digitally-Assisted Analog/RF Testing for Mixed-Signal SoCs," in Proceedings of 17th Asian Test Symposium (ATS2008) , pp.43-48, Sapporo, November 2008. [2] Hsiu-Ming (Sherman) Chang, Kuan-Yu Lin, Chin-Hsuan Chen, and Kwang-Ting (Tim) Cheng, "A Built-In Self-Calibration Scheme for Pipelined ADCs," in Proceedings of 10th IEEE International Symposium on Quality Electronics Design (ISQED2009), pp. 266-271, San Jose, California, March 2009. [3] Hsiu-Ming (Sherman) Chang, Chin-Hsuan Chen, Kuan-Yu Lin, and Kwang-Ting (Tim) Cheng, "Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC, " in Proceedings of 27th IEEE VLSI Test Symposium (VTS2009), pp. 291-296, Santa Cruz, California, May 2009. [4] Hsiu-Ming (Sherman) Chang and Kwang-Ting (Tim) Cheng, "TAC: Testing Time Reduction for Digitally-Calibrated Designs," in Proceedings of 15th IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW2009), pp. 1-6, Scottsdale, Arizona, June 2009. [5] Hsiu-Ming (Sherman) Chang, Kuan-Yu Lin, and Kwang-Ting (Tim) Cheng, "Calibration as a Functional Test: An ADC Case Study," inProceedings of 18th Asian Test Symposium (ATS2009), pp.85-86, TaiChung, Taiwan, November 2009. [6] Hsiu-Ming (Sherman) Chang, Kuan-Yu Lin, and Kwang-Ting (Tim) Cheng, "Calibration-Assisted Production Testing for Digitally-Calibrated ADCs," in Proceedings of 28th VLSI Test Symposium (VTS2010), pp. 295-300, Santa Cruz, California, April 2010. [7] Hsiu-Ming (Sherman) Chang, Kuan-Yu Lin, and Kwang-Ting (Tim) Cheng, "Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study," Journal of Electronic Testing - Theory and Application (Special Issue on Analog, Mixed-Signal and RF Testing), vol. 26, no. 1, pp. 59-71, February 2010 . (SpringerLink) l Application-Aware Quality Management for 3D ICs In [8], we developed an error tolerance scheme for a three-dimensional (3D) CMOS image sensor that is constructed by stacking a backside-illuminated image sensor array, an ADC array, and an image processor array. For a case study based on an architectural level simulation, the error tolerance scheme demonstrates an improvement of effective yield from 46% to 99% in the presence of multiple ADC or through silicon via (TSV) failures. Related Publication: [8] Hsiu-Ming (Sherman) Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, and Cheng-Wen Wu, "An Error Tolerance Scheme for 3D CMOS Imagers," in Proceedings of 47th IEEE/ACM Design Automation Conference (DAC2010), pp.917-922, Anaheim, CA, June 2010. l BIST and BIST-Assisted Tuning for Direct Frequency Modulators In [9], we developed a two-point direct frequency modulator for GSM/EDGE/GPRS based on an analog-enhanced, all-digital PLL architecture. To minimize the modulator error, we proposed a built-in self-test (BIST) technique that can be used to tune the modulator’s performance. The measurement result on a 1.2V 65nm silicon prototype, presented in [10], shows that the test time of the BIST scheme is less than 50μsec and the reported test result is within 1% error in comparison of the measurement data. For the popular sigma-delta fractional-N RF PLLs, the added circuitry required for this BIST solution is all-digital except a bang-bang phase-frequency detector, which incurs an area of only 0.0001mm2 for our implementation in a 65nm CMOS technology. The BIST scheme can be further applied to tune the circuit performance for reducing the modulation error of the modulator to meet the GSM specifications [10]. In [11], we developed a BIST technique to characterize the error transfer function of RF PLLs. This BIST scheme, with on-chip stimulus synthesis and response analysis completely done in the digital domain, achieves high-accuracy characterization and is applicable to a wide range of PLL architectures. Related Publications: [9] Ping-Ying Wang and Hsiu-Ming (Sherman) Chang, "A Charge Pump-Based Direct Frequency Modulator," in Proceedings of 2008 International Symposium on Circuits and Systems (ISCAS 2008), pp. 1962-1965, Seattle, Washington, May 2008. [10] Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, and Hsiu-Ming (Sherman) Chang , "A Digital Intensive Fractional-N PLL and All Digital Self-Calibration Schemes," IEEE J. of Solid-State Circuits (JSSC), vol. 44, no. 8, pp. 2182 - 2192, August 2009. (IEEEXplore) [11] Ping-Ying Wang, Hsiu-Ming (Sherman) Chang, and Kwang-Ting (Tim) Cheng, “An All-Digital Built-in Self-Test Technique for Transfer Function Characterization of RF PLLs,” in Proceedings of Design, Automation and Test in Europe (DATE2011), Grenoble, France, March 2011. l Tutorial papers In [12], we describe the recent development in the test strategies for continuous-time and digitally-assisted adaptive equalizers, which are increasing popular in commercial products. This tutorial paper describes general techniques for testing the adaptive equalizers, as well as test techniques targeting specific design styles. In [13], we review the recent advances in analog, mixed-signal, and RF testing. In addition to describing conventional test methods and BIST techniques, we also emphasize emerging low-cost test paradigm such as loopback testing, alternate testing, and digitally-assisted testing. Related Publications: [12] Kwang-Ting (Tim) Cheng and Hsiu-Ming (Sherman) Chang, "Test Strategies for Adaptive Equalizers," in Proceedings of the 29th Custom Integrated Circuits Conference (CICC2009), pp. 597-603, San Jose, September 2009. (invited) [13] Kwang-Ting (Tim) Cheng and Hsiu-Ming (Sherman) Chang, "Recent Advances in Analog, Mixed-Signal, and RF Testing," IPSJ Transactions on System LSI Design Methodology (TSLDM), vol. 3, pp. 19-46, February 2010. (invited) (IPSJ TSLDM Site) |