***Back to home page:  Dr. Hasan Nayfeh

Talks

•  Invited Speaker: Nanostructured Advanced Materials Sponsored by the NSF Amman-Jordan . "Towards the Smallest Transistor: http://people.physics.uiuc.edu/nayfeh/agenda.html
• Invited speaker: IEEE RTP 2007 Conference: "Channel Strain Engineering for High Performance CMOS Technology" http://www.ieee-rtp.org/ HMNAYFEH_RTP2008_Sep30_2008.pdf
• “eSiGe for 45-nm High Performance SOI CMOS”, IBM SRDC East Fishkill, NY  Think Friday Seminar. September 2007
• "Hole Transport in Nanoscale pFET SOI devices under High Strain", IEEE Device Research Conference- DRC 2007, University of Notre Dame, South Bend, IN, June 2007.  DRC_HMNayfeh_June18_2007v2.pdf
• “Channel Strain Engineering of the 45-nm SOI High Performance Technology PFET MOSFET Device” IBM TJ Watson Research Center Yorktown Heights, NY Exploratory Devices and Integration Seminar. May 2007
• “Investigation of the Electron Transport and Electrostatics of Si/SiGe Strained Silicon Heterostructure MOSFETs” INTEL Corporation, Hillsboro, OR Oct 2003
• “Investigation of the Electron Transport and Electrostatics of Si/SiGe Strained Silicon Heterostructure MOSFETs” Texas Instruments, Dallas, TX Aug 2003
• “Inversion layer electron mobility in strained-Si n-MOSFETs with high channel doping achieved by ion implantation”, IEEE Device Research Conference- DRC 2002. University of California at Santa-Barbara, Santa-Barbara, CA (UCSB),  June 2002.
• “Impact of Ion Implantation Damage and Thermal Budget on Mobility Enhancement in strained Si n-MOSFETs”, 2003 Electronic Materials Conference University of Utah, Salt Lake City, June 2003
•   Panel Participant: IEEE 2002 DRC Rump Session: “Si +??: Strain, Ge, III-V, Etc. – What to do When Scaling Ends”, University of California at Santa Barbara (UCSB), Santa-Barbara, CA, May 2002.
• “Investigation of Scaling Methodology of Strained Si n-MOSFETs using a Calibrated Transport Model”, 2003 IEEE Electron Devices Meeting, Washington D. C. December 2003  hnayfehiedm2003.ppt