Back to home page:  Dr. Hasan Nayfeh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• H. M. Nayfeh, M. Kumar, S. Fang, J. Kedziersky, C. Cabral,  “METAL GATE MOSFET BY FULL SEMICONDUCTOR METAL ALLOY CONVERSION”  US 7,151,023 Dec 19, 2006 US07151023__.pdf  A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that   is  thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region    but only thick enough to partially convert the semiconductor gate stack to a semiconductor metal alloy in a second MOSFET type region. In one embodiment, the gate stack in a first MOSFET region is recessed prior to forming the metal-containing layer so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer is thinned over one MOSFET region relative to the other MOSFET region prior to the conversion process.
• J. R. Holt, E. C. Harley, K. Tabakman, S. Jeng, H. M. Nayfeh,  A. Dube, J. Kempisty (Filed to the USPTO) Abstract- Novel 2-step low/high H2 flow eSiGe deposition for improved narrow width epi fill and improved device sensitivity. One of the major issues with the "early" eSiGe integration scheme is the device sensitivity to the eSiGe fill level.  This sensitivity results in the need to carefully control the epi morphology in order to avoid the epi "popping" up the spacer edge.  However, the same process conditions that can control the epi popping up the spacer can result in an underfilled epi morphology in the narrow width device (eg - SRAM). By using a 2-step deposition recipe, we set the initial growth condition in such a way as to fill the narrow width device.  Then just before the epi reaches a flush fill condition we switch to a growth condition that favors a "pinned" morphology at the spacer edge.  This achieves both a good narrow width device fill as well as a reduced sensitivity to device fill.  
•     H. M. Nayfeh, A. Waite  “STRUCTURE AND METHOD FOR REDUCING MILLER CAPACITANCE IN FIELD   EFFECT TRANSISTORS, US  Patent 20070117334 (published), May 5, 2007 Abstract- A method for forming a field effect transistor (FET) device includes forming a gate conductor and gate dielectric on an active device area of a semiconductor wafer, the semiconductor wafer including a buried insulator layer formed over a bulk substrate and a semiconductor-on-insulator layer initially formed over the buried insulator layer. Source and drain extensions are formed in the semiconductor-on-insulator layer, adjacent opposing sides of the gate conductor, and source and drain sidewall spacers are formed adjacent the gate conductor. Remaining portions of the semiconductor-on-insulator layer adjacent the sidewall spacers and are removed so as to expose portions of the buried insulator layer. The exposed portions of the buried insulator layer are removed so as to expose portions of the bulk substrate. A semiconductor layer is epitaxially grown on the exposed portions of the bulk substrate and the source and drain extensions, and source and drain implants are formed in the epitaxially grown layer.
• B.Y. Kim, S. Jeng, H. M. Nayfeh, X. Chen, “Interface Sealed Proximity eSiGe MOS transistor and fabrication method” (Filed to the USPTO) As one of means for transistor S/D is replaced by the strained mateial (eSiGe) with the eSiGe edge close to gate poly.  However, as the edge of eSiGe close to gate edge, a part of gate oxide (at the edge of poly) is exposed with epi pre-clean and  caues parasitic short between gate poly and substrate(eSiGe), causing  device failure. This disclosure describes a process that results in sealing the gate stack prior to the HF pre-clean that is executed prior to SiGe epitaxy growth.
•    B. Y. Kim, S. Jeng, H. M. Nayfeh, X. Chen, “Nitride Liner Surrounded Facetless eSiGe MOSFET Structure” (Filed to the USPTO) As a means of MOSFET transistor performance boost, embedded SiGe is widely used.  However, due to epitaxial process nature, STI bounded S/D region has fecet  reducing eSiGe benifit. Considering that lots of critical devices are STI bounded, maintaining of  STI bounded transistor performance is important for overall performance enhancement.