Biography of
Brian T. Kelley, PH.D. The University of Texas at San Antonio Email: Brian.Kelley@utsa.ed Academic Education Georgia Institute of
Technology: Presidential Fellow Communications, DSP, Computer Engineering Georgia Inst. Of Tech Thesis Adviser: Vijay Madisetti (U.C. Berkeley)
Georgia Institute of Technology: Office of Naval Research Fellow MSEE School of Electrical Engineering, Atlanta, GA, 1989, DSP, comm. Computer-Eng, Math Minor
Cornell University College of Engineering: Tau Beta Pi & Eta Kappa Nu, Ithaca, NY, 1987, Kodak Scholarship BSEE; Major:
Communications & Signal Processing Academic Appointments University of Texas at San Antonio (UTSA): Assistant Professor of Electrical Engineering in Wireless Communications 2007
EE5283: Fall 2007 (GRAD) Topics in 4G Wireless University
of Texas at Austin: Adjunct Assoc. Prof. of Elec.
Engineering: 2000-2007 EE313:15125 (UGRAD) Linear Signals and Systems: 2002
Honors, Awards, and Fellowships § Associate Editor of Computers & Electrical Engineering, Elsevier, 2008 § Workshop Organizer and Presenter at the IEEE Workshop on "Advances in 3GPP LTE" at the 2009 IEEE Radio and Wireless Conference in San Diego, CA, January, 2009. § Senior Member of the IEEE, 2006 § Engineer of the Year Award: Modern-Day Technology Leader, CCG, 2004
Industrial
R&D Experiences: Motorola & Freescale Launched by Motorola:…………………………..
2006-2007: Freescale representative and contributor to the
3GPP Radio Access Network (RAN1 and RAN4) standards body for development of
next generation HSPA and LTE cellular standards (traveled to world-wide
meetings in Shanghai, Tallin, Riga, & St. Louis).…………………………………………….-…………………………………………... 2005-2007: Freescale Senior Technical leader in the
development of end-to-end system level radio
link level and system level simulators using Matlab classes and object oriented
programming for 3GPP Long Term Evolution (4G LTE), High Speed Packet Access
(3.5G). Systems including both uplink LTE/HSPA and downlink. The next
generation 3GPP standards for 3.5GHSPA/4GLTE were developed and simulated at
the radio link level air interface. 2004-2005: Motorola Technical leader prototype development
of a communication signal processor (CSP) for single antenna interference
cancellation and Edge. 2001-2004: Motorola 802.11 WLAN PROGECT LEADER:
2001-2004
1999-2001: Motorola
SOFTWARE DEFINEABLE RADIO (SDR) PROJECT LEADER: Principal Staff Engineer, Manager, and Technical
project leader of a cross-corporate effort to develop a Software Definable Radio
(SDR) wireless modem to support 3GPP
WCDMA (FDD, TDD), CDMA2000, 1XEV-DO, 1XEV-DV, EDGE, S95B, and GSM.………………………………………. Related Research Publications
Brian Kelley
and Ed Rivas, "OFDM Location-Based Routing Protocols in Ad-Hoc
Networks," to appear in the IEEE
Wireless Hive Conference, Austin, TX, 2008.……………………. Brian Kelley, " GPP Long Term
Evolution Aspects and Migration to 4G Cellular Systems," submitted to the 2009 IEEE
Wireless and Radio Conference, San Diego, CA.………………………………………………………………………………………. Brian Kelley,
"GPS Free Positioning in
Ad-Hoc Wireless Networks Using 4th Generation Mobiles," submitted to the
2008 IEEE Asilomar Conference on Systems, Signals, and Computers, Pacific
Grove, CA.………………………………………………………… Brian Kelley, "Jointly Optimized Software Radio for
Low Power 4G Systems," Proceed. of the IEEE Asilomar Conference on
Systems, Signals, and Computers, 2007. Chang, S., and
Kelley, B.T., “ Time Synchronization for OFDM-based WLAN Systems”, June 2003,
IEE Electronic Letter, Vol 39, No. 13. Kelley, B.T.,
“On Rapid Prototyping and Design of a
Wireless Communication SoC—Delivered Conference Invited Talk”, 1999
IEEE ICCAD/ISSS conference, San
Jose, CA. Kelley, B.T., Johnson, D., "Design Automation of a Receiver: Breaking the RTL Cycle Time Barrier Using (Synopsys) Behavioral Compiler", DesignCon98-BEST PAPER AWARD WINNER, 1998.
Kelley, B.T. “Virtual Bandwidth Digital Receiver Conversion Signal Processor”, MOTOROLA Technical Developments Volume 33, pp. 65-68, December 1997.
U.S. patents (or patents pending): Kelley, B.T., "Blind Channel Adaptive MMSE Edge Equalizer with Space-Time Antenna Interference Cancellation Capability," patent pending Kelley, B.T., “Application Specific DSP Parallel Processor For Single Antenna Interference Cancellation’” patent pending Kelley, B.T., “Generalized Schur Row Pivot & Circular-Hyperbolic Coefficient Extractor With Dynamic Range Detection and Coefficient Auto-scaling”, pat/pend. Satish Kulkarni, Brian Kelley, “Reconfigurable Vector-FFT/IFFT, Vector-Multiplier/Divider for WLAN 802.11 with VLSI Micro-Footprint,” #7,082,451 Kelley, B.T., Chang, Sekchin, “Superlinear Accelerator for Hyperresolution OFDM-WLAN Carrier Frequency Offset Estimation”, 2004, patent # US2004/040926 Kelley, B.T., “A Reconfigurable Rake Pipeline with Multiple Access Interference Suppression,” 2001, #7,187,940 Kelley, B.T., “Adaptive, Multiplier Free Narrow Band Noise Canceller for Spread Spectrum Signaling”, 2000, patent pending Kelley, B.T., Taubenheim, D., Johnson, D. “Temporally Adaptive Signal Classifier apparatus with Perfect Detection Capability”, 1999, patent #6,198,779 Rahman , S., Corleto, J., and Kelley, B.T., “On Chip Fine AFC Using CORDIC Angle Rotation for Digital Receivers”, 1996, #6,192,089. Kelley, B.T., and Bonet, L., “Multiplierless VLSI ROM Mixer for High Rate Digital IF”, 1995, #6,233,287 Kelley, B.T. and Johnson, David M., “Super Scalar Minimum Latency Wallace-MAC with Dual Accumulator Feedback”, US Patent #5847981 on 12/8/98. Kelley, B.T., Fisher, D., and Dao, T., “Method and Apparatus Utilizing Simultaneous Reads for Increasing Memory Bandwidth in a Digital Signal Processor”, 1994, U.S. Patent # 5659695. Kelley, B.T., “Method and Apparatus for a Digital Signal Processor having a Multiplierless Computation Block”, 1994, U.S. patent # 5675822 |