My postgraduate research is mainly on the design of a hardware platform that implements the CPU/FPGA hybrid model. The construction of the platform is carried out in two stages. In the first stage, an i386 PC is connected to an FPGA board via the parallel port to reconfigure FPGA hardware fabric. Such an implementation facilitates system design and the experiments on partial reconfiguration, but introduces high configuration overhead due to low data rate of parallel ports. So in the second stage, we improved the configuration efficiency by connecting an ARM9 architecture chip S3C2440 and the FPGA device via on-chip GPIO port and simulating SelectMAP and JTAG time sequence. Device drivers for configuring FPGA are also developed in Linux operating system. The above two design schemes are both loosely coupled, which means that the CPU and the FPGA work independently with little interaction, thus obstructs the communication and data transfer between software and hardware tasks. This problem can be further resolved by introducing shared memory architecture. I also porting the UC/OS II into the PPC core of XILINX Virtex II pro, and then develop the ICAP device to configure the FPGA internally. A simple hybrid platform has already appeared. 2D partial reconfiguration in Virtex-4 will be developed in following work by using PlanAhead and Early Access Partial Reconfiguration flow.

I also designed the layout within the FPGA fabric to better support a co-design operating system. The FPGA fabric is partitioned into a static OS Frame and dynamic reconfigurable Task Slots. The OS Frame is designed to support communication between FPGA and CPU and its peripherals, and the Task Slots are containers of hardware tasks. The communication among OS Frame and Task Slots is via a TDM (Time Division Multiplexing) Bus Macro to efficiently transfer data and state information. For OS Frame, many communication modules have been implemented, including serial port, SPI and RAM IP cores.

At a higher abstraction level, my research work mainly focuses on HW/SW co-scheduling operating systems. With the introduction of hardware tasks into traditional operating systems, scheduler must be re-designed to support both software and hardware tasks, and to satisfy both real-time constraints and space requirements of tasks. The components that perform scheduling operations are the scheduler and the placer, and my work is tightly related with these components, which includes MER maintenance and dynamic online placement, quantitative evaluation of area fragmentation degree, placement strategies based on task distribution in 2D FPGA model, and improvements of scheduling policies in 1D FPGA model.