There are many requirements such as parallel computing, high frequency architectures, and low power consumption in future SoC designs. Due to the advanced techniques and the multiprocessor designs in recent years, the performance issue is changed from the IP design to the communication architecture. Many well known systems nowadays are builded ased on the bus architectures, which are like AMBA, wishbone, and PLB/OPB bus structures, etc. The major advantage of these bus architecture is easy to implement, while they do not consider the requirements of high bandwidth for multimedia applications and the cooperations between processors. Because of the limited bandwidth of these bus architectures, a novel communication concept of Network on Chip (NoC) is proposed to conquer these drawbacks above and is more suitable for future parallel computing requirements. A basic NoC is organized by routers, links, and processing elements (PEs). The router is used to build the appropriate path to send packets from source PEs to the destination. Routers are composed of a switch, an arbiter, and some buffers. The buffer size in a router is critical to system performance and power consumption. Although NoC is flexible and scalable to multiprocessor architecture, it is complex and the power consumption is still an issue needed to be solved.
|
|
Introduction >
NoC Group |