Research - Interests and Experience

"Love what you do. Do what you love." - Wayne Dyer 

Research Interests :

  • Analog and Mixed Signal VLSI
  • RFIC design
  • Microwave Circuit design
  • System design for communication and biomedical applications
  • Digital Signal Processing
  • Integrated Optics

In addition, I love to read on various other topics like MEMS, Soliton Theory, Fiber Optic Communication, and Quantum Computing, and hope to work on these sometime in the future.

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Graduate Research at OSU :

I am currently pursuing my Ph.D. in Electrical Engineering at the Ohio State University, focusing on High-speed ADCs and DACs, Communication transceivers, Frequency Synthesis, mm-wave circuits, and low-power circuits.

------------------------------RF IC DESIGN--------------------------------

Design of a 3-10 GHz UWB LNA on IBM 90 nm process

The recent interest in continuous bandwidths of operation resulted in my advisor giving our class a project on an UWB LNA. Although switched LNAs or parallel LNAs may be used for each sub-band of operation, it results in stringent settling time requirements and high power consumption. A 3-10 GHz LNA was designed using cascaded cascode amplifiers on IBM 90nm CMOS process. Performance metrics were verified using a buffer at the output. S11 and S22 across the band was achieved to be <-8 dB and <-10 dB respectively, S21 > 20 dB, NF < 5 dB. Current consumption was less than 15 mA from a 1.2 V supply.

Design of a GSM VCO on IBM 90 nm process

We also designed a GSM VCO for the DCS1800 and PCS1900 bands with a phase-noise of <-154 dBc/Hz at 20 MHz. We incorporated sub-banding to limit our Kvco to 40 MHz/V.

Design of a Bluetooth PA on IBM 90 nm process

Our last project was a EDR 2.0 Bluetooth PA. The supply used was 1.2V. The PA was a Class A type, with the spectral mask verified at the input and output for pi/4-QPSK and 8-PSK.

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Low Power IC Design

The increased use of silicon chips for biomedical applications gave me the idea of investigating the best process for these applications and designing a library of circuits out of them. The increased leakage and variability in the advanced processes and no demand in high bandwidths of operation (like cellular applications) makes the 0.18um and 0.13um processes best suitable for biomedical applications. The library of my circuits so far comprises a chopper instrumentation amplifier front-end, a 1V rail-to-rail input-stage OTA, a low-frequency oscillator for pacing applications, a low-voltage-to-high-voltage pacer based on a dickson charge pump architecture, a low-voltage sub-threshold MOS-only voltage reference and a 1 V successive approximation ADC.

Planar Split-Ring Resonators

Ring resonators have gained increasing popularity in the last few years, owing to their high degrees of resonance and huge quality factors. Research on ring resonators have paved way for research on other variants like Split rings and Microdisks. Most of the literature was found to focus on non-planar structures rather than a bus-coupled ring structure. The focus of my work was to investigate bus-coupled planar split ring structures. Fundamental principles were studied more by intuition with necessary qualitative analysis, and the possibilities for split-ring resonator based modulators were investigated. [Report]

Dual Band Wilkinson Power Divider

As part of the ECE710 course, a Dual Band Wilkinson Power Divider, operating at 2 GHz and 4 GHz was designed and fabricated. Optimization of the design was carried out on Agilent ADS. The circuit was fabricated on a Duroid substrate and tested. A power division ratio of 1:1 was observed. Interport isolation was measured to be around -36 dB and -22 dB at 2 GHz and 4 GHz respectively. [Poster]

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Undergraduate Research at CEG, AU:

I was working at the Integrated Systems Laboratory, in College of Engineering, Guindy, Anna University Chennai, under the guidance of Dr. PVR (Dr. P. V. Ramakrishna), during the last two years of my undergrad studies. At this lab, we focused on a complete system design and development and not much on theoretical research.

I worked as a research associate in a team, on India's first university based microsatellite, the ANUSAT, in collaboration with the Indian Space Research Organization, where I am involved in the design, testing and implementation of end to end communication systems from RF front end to Digital back end processing. It was here that I gained exposure to working with FPGAs. I have also assisted the lab in the Thermo-Vac testing of the sub-systems at ISRO, Bangalore.

I was also involved in teaching and guiding my juniors at the ISL with their coursework and projects.

Projects:

ANUSAT Micro-satellite:

ANUSAT Micro-satellite is the first of its kind in India, its specialty being that it is the first university-based micro-satellite project, completely tested and integrated by undergraduate and graduate students of Anna University. The ANUSAT Micro-satellite was primarily started to inculcate the interest of satellite construction and space research among the students by the Indian Space Research Organization. The complete architecture and new schemes employed in its construction, from defining the transmit/receive architectures for telecommanding, and telemeter space-craft data, the protocols for transmission and reception by multiple users on earth, to the integration of the complete satellite were done entirely by students. ANUSAT is also being sent to test FPGA based architectures for the On-board computer, and MEMS based devices. All sub-systems have been designed and tested at Leo Orbit pressure (the orbit level where ANUSAT will be launched into) and temperatures from -15 oC to +50 oC.

ANUSAT took her seat in space on April 20th, after being launched into space by the PSLV rocket from SriHarikota, India at 06:45 IST. ANUSAT would not have been possible without the combined efforts of a number of students of Anna University (Members of the Integrated Systems Laboratory and EEE students at College of Engineering, Guindy and students at Madras Institute of Technology).

All RF systems were designed and tested at the Integrated Systems Laboratory, College of Engineering, Guindy by the students of the lab under the guidance of Dr. PVR, the Project Director of ANUSAT. The integration of the subsystems were also done here, followed by testing at the MIT clean room, again by the students of the lab. 

  • Assisted in the design and test of the on-board Telecommand Receiver that is to receive the command signals from earth, using a dual modulation scheme. An IF of 10.7 MHz. was chosen due to the availability of extremely good SAW filters at that frequency. Down-conversion to 10.7 MHz. is followed by  coherent demodulation with carrier recovered from the RF signal. FSK demodulation is then performed using the chip XR2211. The demodulated data is fed to the FPGA card for decoding and execution. The complete receiver was designed to operate with a sensitivity of -110 dBm and a doppler of +/- 20 kHz.

  • Assisted in the design and test of the on-board Telemetry transmitter, which telemeters the satellite data to earth. It consists of a single up-conversion from 10.7 MHz. The 10.7 MHz. input is a digitally PSK/PM modulated wave from the FPGA and the DAC.

  • Worked on the performance evaluation of the Digital PSK/PM modulation, implemented on an Actel APA 600 FPGA. The phase modulation indices are digitally controlled by the FPGA. This was a good exercise for me to learn the concept of direct digital synthesis and sampling.

  • Designed the complete RF back-end for the Store & Forward transmitter, consisting of a single stage up-conversion of FSK signals at 10.7 MHz. to the transmit carrier frequency. This is used for data communication between multiple users on earth.

  • Designed the All-Digital Store & Forward Receiver, which performs the decoding of FSK signals. A single stage down-conversion to 10.7 MHz. is first done, followed by amplification and subsampling. A DFT based demodulation is then performed on the sub-sampled data to decode the FSK signals. The entire receiver was implemented on the Altera Cyclone II FPGA. The digital baseband receiver was integrated with the RF chain, and tested for a sensitivity of -110 dBm and a doppler of +/- 10 kHz.

  • Involved in the testing of the on-board computer of the satellite - BUS Electronics, in the decoding and deformatting of Manchester coded Telecommand signals.  

The ANUSAT Micro-satellite testing manifested the amount of effort that went into a satellite design and construction. It taught me the importance of isolation of grounds of the sub-systems as well as the power supply, and their influence on the sub-system performance.

Other Projects:

  • Design of a Second order Delta-Sigma ADC

A Continuous-time Delta-Sigma ADC, providing an SNR of 66 dB, was realized on the AMIS 0.35μm CMOS process. A set of high-level specifications had been taken as input and simulations were carried out to evaluate the design performance on MATLAB. The modulator has a single-stage second order architecture. A 2-level quantizer is used in the modulator loop. Individual analog circuit blocks were designed and simulated. The modulator consumes a static power of 116 mW with 20MHz sampling rate. The effects of loop delay were analyzed on Cadence. The bandgap circuit and all biasing circuitry was also designed and integrated. The layouts for the individual modules were drawn on a double-poly five layer metal process and parasitic extraction was carried out. [Presentation]

  • Design of a 12-bit 16MSPS SAR ADC using Cadence Spectre. 

    The SAR ADC operates from a 3V supply. The input signal is sampled at 1MHz. The sample-and-hold circuit feeds the front-end charge redistribution array which realizes the binary search algorithm. The capacitor array feeds a preamplifier for amplification. Three stages of preamplifiers in the telescopic cascode configuration have been designed with offset compensation, and a current consumption of 100uA each. The preamplifiers are then followed by a latch. Auto-zeroing or offset compensation takes two clock cycles and the comparisons take 12 clock cycles. The algorithm for the switching of the charge redistribution array is written at the Macro-level using VerilogA.

  • Design of a MEMS Capacitive Accelerometer using Cadence Spectre

    I focused on the circuit-side implementation of a MEMS Capacitive Accelerometer. The front-end mechanical sensor comprises three parallel plates, of which the middle one is movable and other two plates are fixed. A 1MHz. clock feeds the middle plate. The other two plates are connected to a charge amplifier. The motion of the parallel plates, results in an amplitude modulated signal at 1MHz. carrier frequency. The charge amplifier is a telescopic cascode structure, designed with common mode feedback. Simulations revealed it to have an input referred noise voltage of 6.3nV/√Hz at 1 MHz. The charge amplifier is followed by a mixer to extract the amplitude information. Carrier recovery is not required as the 1MHz carrier is fed to the movable plate from the IC itself. Output of the mixer is filtered using an active filter.

  • Implemented the Linear Kalman filter on the NIOS processor of Altera FPGA. It was implemented as a means of replacing the PLL loop filter and a comparison of its performance over the conventional loop filter was done. Carrier synchronization using the Extended Kalman filter is also being looked at. 
     
  • Worked towards the implementation of an Ultrasound Medical Imaging System design, in conjunction with Texas Instruments. This project will look at the implementation of an end-to-end ultrasound system, along with digital beam-forming techniques, and different modes of scanning for the display. This project is focussed at determining the critical issues involved in the design of an Ultrasound SOC. A single-chip Ultrasound system implementation might also be proposed.

Academic Projects:

  • Presented a stall, along with my friends on the invention of Blue-ray discs and high definition television, for the National technical symposium, Vision '05. It was not exactly a project, but a good start for us.
  • Designed an IR transmitter-receiver for remote-controlled operation of devices. This was my first exposure to practical electronics. This was part of an E-room design by our class, where everything from switching on lights to automated doors was done using discrete components.
  • Designed a metal detector and an electronic polling booth using discrete components, as part of a sophomore project.
  • As a hobby project, I implemented a Numerically Controlled Oscillator using the ATMEL 89C52 micro-controller, for generation of sinusoidal, square, triangular and saw-tooth waves.
  • As a hobby project, I also worked on a music morphing project, as a part of a computerized carnatic music synthesizer. The morphing algorithm was tested for single-tone inputs.
  • Implemented an FSK/AM modulation on a micro-controller, as a demonstration of transmitter architecture of digital radios.

Papers / Posters:

  • Presented a poster on the Mathematical analysis of Genomes and sequencing and its applications to protein coding, for Vision '07, National Technical Symposium of Dept. of ECE, CEG, Anna University.
  • Presented a paper for an Industry-defined problem on Field Programmable Analog Arrays, for Vision '07, National Technical Symposium of Dept. of ECE, CEG, Anna University.

 

Last Updated: January 15, 2010