The big I/O print is now ready for the 3D controller. This picture show the backside of the wirewrap print. As you see all my prints are wired manual with fine wires. This is a lot of work but you may change it easy. This I/O board is the global interface from the CPLD MAX II board. 88 I/O lines are avaible. The ATmega328p AVR controller is also on the print. Now up to the final software. There are 3 modules, 1 for the CPLD board, software written into verilog code, and 2 AVR controllers software written into assembler. As planned I hope to be ready next week 15 March. On the left side the 20 pins connector is only for debugging. The logic analyser can be connected to this connector. All signals from the CPLD board but also from the 2 AVR boards can be routed via this connector for analyse. Next week I will give some pictures of the debugging setup. All software update is done via a USB link and take only a few seconds. Hardware debugging is realtime. The logic analyser is the Intronix LA with 34 channels at 500 Mhz. The software tools for the AVR controllers is the STK600 toolkit. All prints can stay into the setup during debugging or update.

I still need to write a bunch more Verilog in order to actually store and retrieve patches that will be applied to RAM- but as a proof-of-concept, I just hardcoded an address and a single word of data to repeat across an entire cache line. Here it's overwriting an in-memory string with all "x"es.