MSP-430 Reference Information

Reference pages on the MSP-430 Instruction Set

To avoid cognitive overload, the instruction set and its addressing modes are presented incrementally.  These reference pages reflect the order and scope in which content is presented during the course. 

EZ-430 "USB  Stick Development Tool" 

TI Documentation

  • MSP430x20x1, MSP430x20x2, MSP430x20x3 MIXED SIGNAL MICROCONTROLLER  http://www.ti.com/lit/ds/slas491h/slas491h.pdf
    • Information for on this particular version of the MSP430
    • Most info in the "short-form description"
      • Memory map p 15
        • Flash 
          • for programs and interrupt vectors: F800..FFFF (0x800=211=2k bytes)
          • with configuration parameters set by TI such as constants for the clock generator: 0x1000-0x10ff (0x100=28 = 256 bytes)
        • Ram: 0x200..0x280 (0x80=27=128 bytes)
        • I/O devices (peripherals): 
          • 8-bit: 0-0xff (256 addresses)
          • 16-bit: 0x100-0x1ff (256 addresses)
      • Clock system p16
        • Idea: constants used to set clock frequency are stored in flash memory.
        • Set clock frequency by storing them into corresponding registers of the clock module (described in the the users' manual)
      • Interrupts
        • Interrupt vector addresses p 13
        • Interrupt controller registers (in memory) p 14
    • I/O peripheral address map: p19 
    • Memory map: p 15
    • Setting the Digitally Controlled Oscillator (DCO): 
      • Default frequency ~1.1MHz
      • Addresses where constants to set frequency accurately are stored: p 16
      • Registers to control clock p 5-13 
  • MSP430x2xx users guide (slau144)
    • Information abut the family for programmers
    • CPU (section 3)
      • Registers 3-4 (p44-48)
      • Instruction set
        • 1-page summary: 3-75 (p115)
        • Cycles/instruction 3-72, 3-73 (p112,113)
        • Details about each instruction: starts p 3-17 (p57)
          • RLC (rotate left through carry) on 3-59 (p99)
            • emulated using ADDC
          • RLA (rotate left arithmetically)
            • emulated using ADD
          • Rotate right (RRA, RRC) p 3-60..61 (p100-101)
          • Emulated using mov & indirect-post-increment
            • RET, POP (3-56, 3-54)
    • Ch 8: digital IO
      • Description of PxIN, PxOUT, PxDIR on 8-3 (p361)
    • Ch10/11: counter/timers0
    • Ch 5: clock module (sets the clock freq)
      • 5-3 (p289): schematic diagram
      • 5-13 (p299): memory addresses of control registers
      • 5-14 (p300): functions of bits in control registers
    • See p 3-72 (pdf page 112)  for info on instruction timings (cycles/instruction).
  • Scanned documents (from above, handouts from class):
    • I/O subsystems for ports and clock  frequency generator  io-sheets.pdf
    • Documentation on instruction timing, registers, etc.  cpu-sheets.pdf
Online assembler
  • This web page will assemble a single instruction and provide instruction timings: http://mspgcc.sourceforge.net/assemble.html
  • Note that students are encouraged to use it to check their work as that they will not have access to this online tool during an exam. 

MSPGCC docs

The full MSP430 Instruction Set, Addressing Modes, and Registers

This information is presented incrementally during the course. 

Notes relevant to our lab assignments