Apala Guha, Pietro Cicotti, Allan Snavely, Andrew Chien. "The 10x10 Foundation for Heterogeneity: Clustering Applications by Computation and Memory Behavior," University of Chicago Technical Report TR-2012-01. February 2012. Apala Guha, Kim Hazelwood, Mary Lou Soffa. “Memory Optimization of Dynamic Binary Translators for Embedded Systems,” To appear in Transactions on Architecture and Code Optimization (TACO). Apala Guha. “Memory Optimization of Dynamic Binary Translators for Embedded Platforms,” Ph.D. Thesis, School of Engineering and Applied Science, University of Virginia, August 2010. Apala Guha, Kim Hazelwood, Mary Lou Soffa. “Balancing Memory and Performance through Selective Flushing of Software Code Caches,” International Conference on Compilers Architecture and Synthesis for Embedded Systems (CASES), Scottsdale, AZ, October 2010. Best Paper Nominee! Apala Guha, Kim Hazelwood, Mary Lou Soffa. “DBT Path Selection for Holistic Memory Efficiency and Performance,” ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE), Pittsburgh, PA, March 2010. Apala Guha, Kim Hazelwood, Mary Lou Soffa. “Code Lifetime-Based Memory Reduction for Virtual Execution Environments,” 6th Workshop on Optimizations for DSP and Embedded Systems (ODES) held in conjunction with the 2008 International Symposium on Code Generation and Optimization (CGO) Boston, MA, April 2008. Apala Guha, Jason D. Hiser, Naveen Kumar, Jing Yang, Min Zhao, Shukang Zhou, Bruce R. Childers, Jack W. Davidson, Kim Hazelwood, Mary Lou Soffa. "Virtual Execution Environments: Support and Tools," NSF Next Generation Software Program Workshop (NSFNGS) held in conjunction with the International Parallel and Distributed Processing Symposium (IPDPS), Long Beach, CA, March 2007. Apala Guha, Kim Hazelwood, Mary Lou Soffa. “Reducing Exit Stub Memory Consumption in Code Caches,” International Conference on High Performance Embedded Architectures and Compilers (HiPEAC), Ghent, Belgium, January 2007. |