My primary interests span computer architecture and systems, particularly in system-level parallelism, large-scale graph processing, cache and memory architectures, binary rewriting, virtual machines and formal verification. I am currently a post-doc in the Computer Architecture Group at the University of Cambridge Computer Laboratory, looking at ways to reduce power consumption in CPU caches.  Background
I spent a short while at Acunu where I worked on analysing the performance of their filesystem.
I finished my PhD in June 2011 from the Networks and Operating Systems (NetOS) research group at the Computer Laboratory in the University of Cambridge. I was supervised by Steven Hand and Tim Harris. My PhD thesis, titled "Software lock elision for x86 machine code", argues for separation of mechanism and policy in the context of software transactional memory. It presents the design and implementation of a system that can be used to automatically elide legacy locks in x86 machine code. Transactional memory therefore becomes an optional mechanism for synchronisation, with legacy locks or atomic blocks implemented using legacy locks being used to specify synchronisation policy. A talk I gave at MSR describes many of the basic ideas.
I used to work at Intel till August 2007 where I worked for some time on memory consistency verification and later did performance modeling and analysis of CPUs. Among other things, I designed a parallel algorithm to verify memory consistency test results using graphs, which is widely used in Post Silicon validation at Intel. More work related things can be found in my linkedin profile.
I got my undergraduate engineering degree at Jadavpur University in the Department of Computer Science and Engineering. Publications [my google scholar profile]
Amitabha Roy, Steven Hand, Tim Harris: Hybrid Binary Rewriting for Memory Access Instrumentation, VEE 2011
Amitabha Roy, Steven Hand, Tim Harris: Poster: Weak Atomicity Under the x86 Memory Consistency Model, PPoPP 2011
Amitabha Roy, Steven Hand, Tim Harris: A Runtime System for Software Lock Elision, Eurosys 2009
Amitabha Roy, Steven Hand, Tim Harris: Exploring the Limits of Disjoint Access Parallelism, HotPar 2009
Technical Reports
Amitabha Roy: Memory Hierarchy Sensitive Graph Layout, Arxiv 2012
Teaching
I've acted as a TA for a graduate level Operating systems course at IISc, supervised undergraduate students at Cambridge for the Part II Comparative Architectures course and delivered part of a mini-course on lock-free programming and transactional memory.
Contact
amitabha dot roy at cl dot cam dot ac dot uk amitabha dot roy at gmail dot com
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