In Verilog, a declaration of reg is for a variable which can be assigned in a sequential (always) block. A reg declaration does not imply that a hardware Register or a Flip-Flop will be created for this variable. It may be the case that a register is created by a synthesis tool for a variable declared as a reg, but the structure of the Verilog program determines how a variable is synthesized.

In Verilog for RTL synthesis, registers (flip-flops) are modeled and inferred by a sequential always block which has a basic structure such as:

       reg [5:0] state, next_state ;
       always @(posedge clk)
              state <= next_state ;

Even though both state and next_state are declared as reg, an RTL synthesis tool creates a register for state, and not next_state. With Bluespec, declarations of registers or flip-flops as well as other state elements (such as FIFOs) are explicit by using the mkReg (or mkFIFO for FIFOs) function declarations.

       // Create 6 bit wide register with a 0 reset value
       Reg #(Bit#(6)) state <- mkReg (0) ;     // Create a register with interface state
 
       // Create a FIFO interface and fifo
       FIFO #(Bit#(6)) input_fifo <-  mkFIFO ;

Note that in the Bluespec example, the Register and its interface are declared, but the specifics of the inputs, outputs, clock and reset port connections are not described; this task is handled by the compiler. The reading and writing of Bluespec registers, FIFOs, and other modules is accomplished through their interface methods in rules or interface methods.