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Can you assume that the rule guards (conditions) are always mutually exclusive with one-at-a-time semantics? Discussion here.

When you have multiple rules communicating with RWires, the resulting behavior may seem contrary to your expectations.  Check out the section "RWires and Atomicity", on the Rules of Wires page.

We've added a new tutorial on using importBVI to wrap an RTL model (Verilog or VHDL) for use in a BSV design.  Download the paper only, or a tar file including code examples along with the paper.

Learning Bluespec and Basic Concepts

This is the place to go if you are a new user or prospective user and want to learn more about Bluespec and Bluespec SystemVerilog.  For an overview of Bluespec, see our Product information.

Small Examples

This is a series of small BSV examples to illustrate various language concepts in Bluespec SystemVerilog (BSV). Each example is as small as possible, illustrating just one concept (goal: one page or less of BSV code).

This set of examples is a freely available reference resource for the Bluespec community (mainly users, but even the just curious are welcome to browse). The examples can be read linearly in the sequence given, or randomly according to interest, because each example is a complete, self-contained, executable BSV program.

Detailed Examples and Design Techniques

This section contains more detailed examples and design techniques recommended for more experienced users.

Installation Guide

This section includes system requirements and licensing information.

BSV Documentation